Test MP+dmb.sy+pos-addr-data-[ws-rf]-addr

AArch64 MP+dmb.sy+pos-addr-data-[ws-rf]-addr
"DMB.SYdWW Rfe PosRR DpAddrdR DpDatadW WsLeave RfBack DpAddrdR Fre"
Cycle=Rfe PosRR DpAddrdR DpDatadW WsLeave RfBack DpAddrdR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR DpDatadW [WsLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe PosRR DpAddrdR DpDatadW WsLeave RfBack DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X7=a; 1:X11=x;
2:X1=a;
}
 P0          | P1                    | P2          ;
 MOV W0,#1   | LDR W0,[X1]           | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]           | STR W0,[X1] ;
 DMB SY      | EOR W3,W2,W2          |             ;
 MOV W2,#1   | LDR W4,[X5,W3,SXTW]   |             ;
 STR W2,[X3] | EOR W6,W4,W4          |             ;
             | ADD W6,W6,#1          |             ;
             | STR W6,[X7]           |             ;
             | LDR W8,[X7]           |             ;
             | EOR W9,W8,W8          |             ;
             | LDR W10,[X11,W9,SXTW] |             ;
Observed
    y=1; x=1; a=2; 1:X8=1; 1:X2=0; 1:X10=1; 1:X0=1;
and y=1; x=1; a=1; 1:X8=1; 1:X2=0; 1:X10=1; 1:X0=1;